(a) Field of the Invention
This inventive concept relates generally to discrete capacitance design, and more specifically, to a switched-capacitor circuit, a radio frequency device, and a switched-capacitor circuit manufacturing method.
(b) Description of the Related Art
Differential signal is one of the most frequently used signals in a radio frequency circuit. Two differential ports of a differential signal are commonly connected to switched capacitors and on-chip inductors for frequency tuning to achieve high resistance in a narrow frequency band, and thus realize functions such as signal amplification and signal filtering. As a result, differential switched capacitors are commonly used in radio frequency circuit modules such as operational amplifier, voltage controlled oscillator, low noise amplifier, and frequency mixer.
A switched-capacitor circuit has two work modes: an “ON” mode and an “OFF” mode. A well-designed radio frequency switched-capacitor circuit will have as small as possible on-resistance in “ON” mode to achieve a high quality factor (the “Q value”), while maintaining as small as possible parasitic capacitance in “OFF” mode to minimize the parasitic effect of the switched capacitor modular.
FIG. 1 shows a diagram illustrating a conventional switched-capacitor circuit. In “ON” mode, this circuit has an equivalent on-resistance of Ron×2, twice the on-resistance Ron of a single Metal Oxide Semiconductor (MOS) transistor, therefore it has a low Quality factor.
FIG. 2 shows a diagram illustrating another conventional switched-capacitor circuit. In this circuit, a switch control signal D is connected to a gate of a first N-type Metal Oxide Semiconductor (NMOS) transistor N1, a gate of a second NMOS transistor N2, an input node of a first inverter 001, and an input node of a second inverter 002. A first node of a first capacitor C1 is connected to a drain of the first NMOS transistor N1, and a second node of the first capacitor C1 works as a first output node P. An output node of the first inverter 001 is connected to a first node of a first resistor R1, and a second node of the first resistor R1 is connected to the drain of the first NMOS transistor N1, a first node of the second capacitor C2 is connected to a drain of the second NMOS transistor N2, and a second node of the second capacitor C2 works as a second output node N. An output node of the second inverter 002 is connected to a first node of the second resistor R2, and a second node of the second resistor R2 is connected to the drain of the second NMOS transistor N2, a drain of a third NMOS transistor N3 is connected to the drain of the first NMOS transistor N1, a source of the third NMOS transistor N3 is connected to the drain of the second NMOS transistor N2, and a gate of the third NMOS transistor N3 is connected to a digital control signal D.
Compared to the circuit of FIG. 1, the circuit of FIG. 2 has a smaller parasitic capacitance in “OFF” mode. However, the circuit of FIG. 2 involves more circuit components and therefore is more complicated than that of FIG. 1. Also, in “OFF” mode, drain parasitic capacitances of the first NMOS transistors N1 and the second NMOS transistor N2 are introduced to the first capacitors C1 and the second capacitor C2, respectively, which increases the parasitic capacitance of the circuit.